A. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a trench gate insulated gate bipolar transistor (IGBT).
B. Description of the Related Art
A technique for reducing the power consumption of a power conversion device has been developed and there are great expectations for a technique for reducing the power consumption of a power device which plays a central role in the power conversion device. Among the power devices, an insulated gate bipolar transistor (IGBT) which can reduce an on-voltage using a conductivity modulation effect and is easily controlled by the control of a voltage-driven gate is generally used.
As a MOS gate (an insulated gate with a metal-oxide-semiconductor structure) structure of the IGBT, the following have been known: a planar gate IGBT in which a gate electrode is provided along the surface of a wafer, and a trench gate IGBT in which a polysilicon gate electrode is provided on the inner wall of a trench with a shape that extends from a stripe-shaped planar pattern on the surface of wafer in a direction perpendicular to the depth direction, with a surface oxide film interposed therebetween. In the trench gate IGBT, since a channel is formed along both inner side walls of the trench in which an opening portion is the stripe-shaped planar pattern, the opening width of the trench and the spacing of the stripe-shaped trench pattern are reduced to increase channel density to be higher than that in the planar gate IGBT. When the channel density is increased, it is possible to further reduce the on-voltage. Therefore, in recent years, the use of the trench gate IGBT has increased.
Next, the structure of a general trench gate IGBT will be described. FIG. 8 is a cross-sectional view illustrating a trench gate IGBT with a floating potential region according to the related art. In FIG. 8, a p layer 112 including a p base region 103 and a floating p region 111 is formed in a surface layer of the front surface (close to an n− drift layer 102) of a silicon substrate in which the n− drift layer 102 is formed on the front surface of a p+ silicon substrate that will be a p+ collector region 101. The p layer 112 is divided into the p base region 103 and the floating p region 111 by a plurality of trenches 110 which extend from the front surface of the silicon substrate to the n− drift layer 102 through the p layer 112.
The p base region 103 is interposed between the side walls, which are close to a portion of the p layer 112 in which the n+ emitter region 104 is provided, of the adjacent trench 110. Since a main current flows in the region that is interposed between the side walls, which are close to the portion in which the n+ emitter region 104 is provided, of adjacent trenches 110, the region is also referred to as an active mesa region. The floating p region 111 is interposed between the side walls, which are close to a portion of the p layer 112 in which the n+ emitter region 104 is not provided, of adjacent trenches 110. The floating p region 111 is insulated from the n− drift layer 102 by a pn junction with the n− drift layer 102 and is insulated from a gate electrode 106 by a gate insulating film 105. That is, the floating p region 111 is in a so-called floating state (floating region).
The gate electrode 106 is provided on the inner wall of the trench 110, with the gate insulating film 105 interposed therebetween. The n+ emitter region 104 comes into contact with the gate insulating film 105 provided on the side wall of the trench 110 which is close to the p base region 103. An emitter electrode 108 is electrically connected to the n+ emitter region 104 and the p base region 103 and is insulated from the gate electrode 106 by an interlayer insulating film 107. In addition, the emitter electrode 108 is covered with a passivation film (not shown) which is a silicon nitride film (Si3N4 film), an amorphous silicon film, or a polyimide film. A collector electrode 109 comes into contact with the p+ collector region 101.
Next, the operation of the IGBT shown in FIG. 8 will be described. First, an operation of changing the trench gate IGBT from an off state to an on state will be described. The emitter electrode 108 is generally connected to the earth. When the voltage of the gate electrode 106 is lower than a threshold value, with a voltage higher than that of the emitter electrode 108 being applied to the collector electrode 109, the pn junction between the p base region 103 and the n− drift layer 102 is reversely biased. Therefore, no current flows between the emitter and the collector. That is, the IGBT is turned off.
When a gate driving circuit (not shown) applies a voltage higher than the threshold value to the gate electrode 106 through a gate resistor, charge starts to be stored in the gate electrode 106. At the same time as the charge is stored in the gate electrode 106, a region, which comes into contact with the trench 110, in a portion of the p base region 103 interposed between the n+ emitter region 104 and the n− drift layer 102, is reversed and an n-type channel region is formed. Then, an electron emitted from the emitter electrode 108 is injected into the n− drift layer 102 through the n+ emitter region 104 and the n-type channel region.
The pn junction between the p+ collector region 101 and the n− drift layer 102 is forward biased by the injected electron and a hole is injected from the collector electrode 109. Therefore, a current flows between the emitter and the collector. That is, the IGBT is turned on. A voltage drop between the emitter electrode 108 and the collector electrode 109 of the IGBT in the on state is the on-voltage.
Next, an operation of changing the IGBT from the on state to the off state will be described. First, the gate voltage between the emitter electrode 108 and the gate electrode 106 is reduced to the threshold value or less. Then, the charge stored in the gate electrode 106 is discharged to the gate driving circuit through the gate resistor. At that time, the n-type channel region returns to a p type and the channel region is removed. Therefore, the supply of electrons from the emitter electrode 108 to the n− drift layer 102 is stopped. As a result, no hole is injected from the collector electrode 109 and the electrons and holes stored in the n− drift layer 102 are respectively discharged to the collector electrode 109 and the emitter electrode 108 or they are recombined with each other to disappear. Therefore, no current flows between the emitter and the collector. That is, the IGBT is turned off.
Various improvement methods have been proposed in order to further reduce the on-voltage of the trench gate IGBT. For example, an IGBT which is called an injection enhanced gate bipolar transistor (IEGT) with limitation characteristics close to the on-voltage of a diode has been known (for example, see the JP 5-243561 (FIG. 101)). In the IEGT device, the surface of an n+ emitter region and a portion of a p base region is covered and insulated by an insulating film to reduce the contact area between the n+ emitter region and the p base region, and an emitter electrode.
The operation of the IEGT is basically the same as the operation of the trench gate IGBT. Holes below the n+ emitter region and the p base region which are electrically insulated from the emitter electrode are less likely to be discharged to the emitter electrode when the IEGT is turned off and are stored in the regions. As a result, the carrier concentration distribution of an n− drift layer is close to the carrier concentration distribution of the diode and the on-voltage is lower than the on-voltage of the general trench gate IGBT.
However, the power device requires high-speed switching characteristics in addition to a low on-voltage and an important challenge is to improve the characteristics. However, in the trench gate IGBT and the IEGT, as the density of the trench structure increases in order to reduce the on-voltage, the capacitance between the gate electrode and the emitter electrode increases and the switching characteristics deteriorate.
When the trench gate IGBT and the IEGT are changed from the off state to the on state, charge is stored in the capacitance between the gate electrode and the emitter electrode. When the trench gate IGBT and the IEGT are changed from the on state to the off state, it is necessary to discharge the charge stored in the capacitance between the gate electrode and the emitter electrode.
Therefore, when the capacitance between the gate electrode and the emitter electrode increases, the charge and discharge time increases. As a result, the switching characteristics deteriorate and switching loss increases. In addition, the total loss of the power device is the sum of steady loss which is determined by the on-voltage and the switching loss which occurs during a switching operation. Therefore, it is important to reduce the on-voltage and to reduce the capacitance between the gate electrode and the emitter electrode in order to reduce the switching loss. When the capacitance between the gate electrode and the emitter electrode is reduced, it is possible to prevent the deterioration of the switching characteristics.
As an IGBT which solves these problems, an IGBT including a floating p region has been proposed (for example, see JP 2001-308327 (FIG. 1)). In JP 2001-308327, the floating p region in a floating state is provided. Therefore, holes are less likely to be discharged to the emitter electrode in the vicinity of a portion below the floating p region when the IGBT is turned off and are stored in the floating p region. As a result, similarly to the above, the carrier concentration distribution of an n− drift layer is close to the carrier concentration distribution of the diode and the on-voltage is reduced. The floating p region is also referred to as a floating mesa region. Since a trench gate structure is not formed in the floating p region, the capacitance between the gate electrode and the emitter electrode is reduced and the charge and discharge time is reduced. It is possible to reduce the switching loss.
M. Yamaguchi et al., “IEGT Design Criterion for Reducing EMI Noise,” in Proc. ISPSD' 2004 pp. 115-118, 2004 (Abstract) discloses a necessity for improving turn-on characteristics which is common to the structure of JP 2001-308327 and the structure of JP 5-243561.
In addition, U.S. Pat. No. 6,815,769 discloses a structure for further improving the turn-on characteristics. That is, a polysilicon layer (gate electrode) which is filled in a trench is divided, only a polysilicon layer which is close to an n+ emitter region and a p base region (active mesa region) is separated and divided as a gate electrode, and a polysilicon layer which is close to a floating mesa region is not connected to a gate electrode, but is connected to an emitter electrode. In addition, U.S. Pat. No. 6,815,769 discloses the following method of dividing the polysilicon layer. A polysilicon layer is formed with a thickness that is not large enough to completely fill the trench. Then, the polysilicon layer on the bottom of the trench is cut using an oxide film as a mask, with the polysilicon layer remaining on the surface of the substrate. Then, for example, an oxide film fills a space between the polysilicon layers in the trench to separate the polysilicon layers on both side walls and a drawing portion to the polysilicon layer on the surface of the substrate is formed (for example, see U.S. Pat. No. 6,815,769 (FIG. 1)).
A horizontal MOS device with the following structure has been proposed: two gate polysilicon layers are provided in a trench so as to be separated from each other; one of the gate polysilicon layers is drawn to another trench which is connected to one side wall of the trench; and the other gate polysilicon layer is drawn to still another trench which is connected to the other side wall of the trench (for example, see the following JP 2010-258005 (FIGS. 2 and 3)).
However, in the method of dividing the polysilicon layer in the trench in order to improve the turn-on characteristics which is disclosed in U.S. Pat. No. 6,815,769, when the gate electrode is formed along both inner walls of the trench, a polysilicon film, which is a gate electrode material, is formed along the inner wall of the trench and the polysilicon film on the bottom of the trench is removed by general photolithography and etching, with the polysilicon film remaining on the front surface of the silicon substrate. In this way, the gate electrode in the trench is divided. Therefore, the number of process steps is too large and there is a concern that costs will increase or yield will be reduced.